1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of Related Art
In recent years, an integration degree of semiconductor devices such as DRAM (Dynamic Random Access Memory) have been enhanced, the gate length of transistors that make up the semiconductor devices has been increasingly reduced. However, as the gate length of the transistors is reduced, the short channel effects of the transistors become apparent, resulting in an increase in subthreshold current. As a result, as for semiconductor devices in recent years, a decline in transistors' threshold voltages (Vt) is considered a problem. To avoid the problem, one option would be to increase the impurity concentration of a semiconductor substrate to curb a decline in transistors' threshold voltages (Vt). In this case, however, another problem arises that a junction leakage current is increased. In memory cells of DRAM, an increase in junction leakage current is a factor in serious deterioration of refresh characteristics.
As a structure to avoid such a problem, each of Japanese Patent Application Laid-Open No. 2006-339476 and Japanese Patent Application Laid-Open No. 2007-081095 discloses a so-called trench gate-type transistor, a transistor in which a gate electrode is embedded in a trench that is formed on a main surface of a semiconductor substrate. The trench gate-type transistor is also called a recess channel transistor. In the trench gate-type transistor, an effective channel length (gate length) can be physically and sufficiently secured. Therefore, the use of the trench gate-type transistors for cell transistors makes it possible to realize a DRAM having minute memory cells whose minimum processing size is less than or equal to 60 nm, for example.
What is disclosed in Japanese Patent Application Laid-Open No. 2007-081095 is a DRAM including: two trenches, which are formed adjacent to each other on a semiconductor substrate; two gate electrodes, which are formed in each trench via a gate insulation film; a first impurity diffusion region, which is formed in a region of a main surface of the semiconductor substrate that is positioned between the two gate electrodes and which is an impurity diffusion region common to the two gate electrodes; and two second impurity diffusion regions, which are formed in a region of the main surface of the semiconductor substrate that is positioned between each of the two gate electrodes and an element isolation region.
In a DRAM having the trench gate-type transistor disclosed in Japanese Patent Application Laid-Open No. 2006-339476 and Japanese Patent Application Laid-Open No. 2007-081095, a channel region of the transistor is formed across three faces, or both sides and bottom of the trench.
The inventors of the present invention found that, if transistors having such a configuration are further miniaturized, it becomes impossible to ensure a sufficient on-state current of the transistors, and it becomes difficult for the DRAM to work properly. The difficulty is considered attributable to high channel resistance caused by that the channel region is formed across the three faces.
Moreover, if an arrangement pitch of trench gates is narrow, an operation state of one transistor interferes with another adjacent transistor when that one transistor is operated. Therefore, the problem becomes obvious that transistors cannot be operated independently. As for the problem, the formation of a channel region between adjacent trench gates is considered to have an adverse effect.
Furthermore, in the trench gate-type transistor, a gate electrode is so formed as to protrude above a surface of a semiconductor substrate. The protruding gate electrode makes it very difficult to form bit lines and capacitors in subsequent processes. As a result, the problem also arises that it becomes difficult to make DRAMs.
Therefore, as for a DRAM that is equipped with transistors that use trenches, what is desired is to ensure a sufficient on-state current of the transistors, as well as to provide a semiconductor device that can prevent operations of adjacent transistors from interfering with each other and eliminate difficulty in production, and a production method thereof.